Landin, Anders and Haridi, Seif and Hagersten, Erik and Andersson, Pär (1991) A performance study of the DDM - a cache-only memory architecture. [SICS Report]
Large-scale multiprocessors suffer from long latencies for remote accesses. Caching is by far the most popular technique for hiding such delays. Caching not only hides the delay, but also decreases the network load. Cache-Only Memory Architectures (COMA), have no physically shared memory. Instead, all the memory resources are invested in caches, resulting in caches of the largest possible size. A datum has no home, and is moved by a protocol between the caches, according to its usage. It might exist in multiple caches. Even though no shared memory exists, the architecture still provides the shared memory view to a programmer. Simulation results from large programs running on 64 processors indicate that the COMA adapts well to existing programs for shared memory. They also show that an application with a poor locality can benefit by adopting to the COMA principle of no home for data, resulting in a reduced execution time of a factor three. In a COMA, a large majority of the misses are invalidation misses, or share misses caused by write-once/read-many behavior, or a producer-consumer relation, i.e. would ben- efit from write broadcast. A new protocol is proposed that behaves like a write-invalidate protocol by default for all data. A reader can detect its need for a write-broadcast behavior for a datum, which it enables by sending a subscribe request for the datum to the writer.
|Item Type:||SICS Report|
|Uncontrolled Keywords:||Multiprocessor, COMA, hierarchical architecture, hierarchical buses, multilevel cache, shared memory, split-transaction bus, cache coherence, cache-only memory architecture|
|Deposited By:||Vicki Carleson|
|Deposited On:||22 Oct 2007|
|Last Modified:||18 Nov 2009 16:00|
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